1. Field of the Invention
The embodiments of the invention generally relate to deep trench capacitors, and, more particularly, to a deep trench capacitor structure having a buried capacitor plate contact simultaneously formed using second deep trench.
2. Description of the Related Art
Deep trench capacitors are often used to add capacitance to various types of integrated circuit devices and structures, including but not limited to memory cells and decoupling capacitor arrays. For example, as disclosed in U.S. Pat. No. 6,507,511, which was issued to Barth et al. on Jan. 14, 2003 and which is incorporated herein by reference in its entirety, deep trench capacitors can be used to add capacitance to the storage nodes of static random access memory (SRAM) cells and other types of memory cells in order to increase Qcrit and eliminate soft errors. Soft errors occur due the movement of alpha particles, which can introduce a charge into a memory cell circuit. Such a charge can cause the logic state of the cell to inadvertently change. Added capacitance to the storage nodes of memory cells reduces their susceptibility to soft errors, by providing increased stability (i.e., by increasing the charge required for the logic state of the memory cell to change). Additionally, as circuits scale for higher speed, larger transient switching noise is generated and more on-chip decoupling capacitance is required. Conventional planar oxide capacitors require more space than desireable; therefore, deep trench capacitors are used to provide the capacitance requirements and the chip size requirements simultaneously.
A typical deep trench capacitor comprises a deep trench in a semiconductor substrate (e.g., the semiconductor substrate of either a bulk silicon wafer or silicon-on-insulator (SOI) wafer). A doped region within in the substrate adjacent to the trench forms one capacitor plate (i.e., a buried capacitor plate). A dielectric layer lining the trench forms the capacitor dielectric. Finally, a conductive fill material (e.g., a doped polysilicon) within the trench forms another capacitor plate. A standard contact can be formed to capacitor plate within the trench. However, a number of additional processing steps are required to form the buried capacitor plate contact.
For example, if a bulk silicon wafer is used, then the deep trench capacitor must be formed such that it extends through an N-doped diffusion connector (e.g., an NWELL) in the silicon substrate. Next, a feature is patterned in the NWELL at the top surface of the silicon substrate and a contact is formed to this patterned silicon feature. Similarly, if a silicon-on-insulator (SOI) wafer is used, then the deep trench capacitor must be formed such that it extends through an N-doped diffusion connector (e.g., an NBAND) below the buried oxide (BOX) layer. Next, a patterned doped polysilicon feature is formed that extends through the BOX layer to the NBAND and a contact is formed to this polysilicon feature.
In either case, due to the requirement of an N-doped diffusion connector, circuit design flexibility is sacrificed. Furthermore, in either case photolithographic techniques must be used to pattern a feature to the N-doped diffusion connector. Consequently, the ground rules for these additional processing steps must take into account overlay tolerances between the contact structures and the deep trench capacitor itself, critical dimension tolerances, the minimum allowable distance between the buried trench and the boundary of the n-doped diffusion connector, etc. Consequently, process windows are small and the sizes of the various circuits that incorporate such deep trench capacitors (e.g., SRAM cells) are not optimized.